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INTEGRATED CIRCUITS
DATA SHEET
PCF8573 Clock/calendar with Power Fail Detector
Product specification Supersedes data of May 1989 File under Integrated Circuits, IC12 1997 Mar 28
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
CONTENTS FEATURES 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 8 8.1 8.2 8.3 8.4 9 9.1 9.2 10 11 12 13 14 15 16 16.1 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 17 18 19 GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Oscillator Prescaler and time counter Alarm register Comparator Power on/power fail detection Interface level shifters CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System configuration Acknowledge I2C-BUS PROTOCOL Addressing Clock/calendar READ/WRITE cycles LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
PCF8573
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
1 FEATURES I2C-bus interface for minutes, hours, 2 GENERAL DESCRIPTION
PCF8573
* Serial input/output days and months
* Additional pulse outputs for seconds and minutes * Alarm register for presetting a time for alarm or remote switching functions * On-chip power fail detector * Separate ground pin for the clock allows easy implementation of battery back-up during supply interruption * Crystal oscillator control (32.768 kHz) * Low power consumption. 3 QUICK REFERENCE DATA SYMBOL VDD - VSS1 VDD - VSS2 fosc 4 PARAMETER supply voltage, clock (pin 16 to pin 15) supply voltage, I2C-bus (pin 16 to pin 8) crystal oscillator frequency ORDERING INFORMATION
The PCF8573 is a low threshold, CMOS circuit that functions as a real time clock/calendar. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The IC incorporates an addressable time counter and an addressable alarm register for minutes, hours, days and months. Three special control/status flags, COMP, POWF and NODA, are also available. Back-up for the clock during supply interruptions is provided by a 1.2 V nickel cadmium battery. The time base is generated from a 32.768 kHz crystal-controlled oscillator.
MIN. 1.1 2.5 - - -
TYP.
MAX. 6.0 6.0 - V V
UNIT
32.768
kHz
PACKAGE TYPE NUMBER NAME PCF8573P PCF8573T DIP16 SO16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil); long body plastic small outline package; 16 leads; body width 7.5 mm VERSION SOT38-1 SOT162-1
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
5 BLOCK DIAGRAM
PCF8573
Fig.1 Block diagram.
6
PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION address input address input comparator output serial data line; I2C-bus serial clock line; I2C-bus enable power fail flag input power fail flag input negative supply 2 (I2C interface) one pulse per minute output one pulse per second output oscillator tuning output test input; connect to VSS2 if not in use oscillator input oscillator input/output negative supply 1 (clock) common positive supply 4 Fig.2 Pinning diagram.
SYMBOL A0 A1 COMP SDA SCL EXTPF PFIN VSS2 MIN SEC FSET TEST OSCI OSCO VSS1 VDD 1997 Mar 28
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
7 7.1 FUNCTIONAL DESCRIPTION Oscillator 7.3 Alarm register
PCF8573
The PCF8573 has an integrated crystal-controlled oscillator which provides the timebase for the prescaler. The frequency is determined by a single 32.76 kHz crystal connected between OSCI and OSCO. A trimmer is connected between OSCI and VDD. 7.2 Prescaler and time counter
The alarm register is a 24-bit memory. It stores the time-point for the next setting of the status flag COMP. Details of writing and reading of the alarm register are included in the description of the characteristics of the I2C-bus. 7.4 Comparator
The prescaler provides a 128 Hz signal at the FSET output for fine adjustment of the crystal oscillator without loading it. The prescaler also generates a pulse once a second to advance the seconds counter. The carry of the prescaler and the seconds counter are available at the outputs SEC, MIN respectively, and are also readable via the I2C-bus. The mark-to-space ratio of both signals is 1 : 1. The time counter is advanced one count by the falling edge of output signal MIN. A transition from HIGH-to-LOW of output signal SEC triggers MIN to change state. The time counter counts minutes, hours, days and months, and provides a full calendar function which needs to be corrected only once every four years - to allow for leap-year. Cycle lengths are shown in Table 1. Table 1 Cycle length of the time counter NUMBER OF BITS 7 6 6
The comparator compares the contents of the alarm register and the time counter, each with a length of 24 bits. When these contents are equal the flag COMP will be set 4 ms after the falling edge of MIN. This set condition occurs once at the beginning of each minute. This information is latched, but can be cleared by an instruction via the I2C-bus. A clear instruction may be transmitted immediately after the flag is set and will be executed. Flag COMP information is also available at the output COMP. The comparison may be based upon hours and minutes only if the internal flag NODA (no date) is set. Flag NODA can be set and cleared by separate instructions via the I2C-bus, but it is undefined until the first set or clear instruction has been received. Both COMP and NODA flags are readable via the I2C-bus.
UNIT minutes hours days(1)
COUNTING CYCLE 00 to 59 00 to 23 01 to 28 01 to 30 01 to 31
CARRY FOR FOLLOWING UNIT 59 00 23 00 28 01 or 29 01 30 01 31 01 12 01
CONTENT OF MONTH COUNTER
2 (note 1) 2 (note 1) 4, 6, 9, 11 1, 3, 5, 7, 8, 10, 12
months Note
5
01 to 12
1. During February of a leap-year the `Time Counter Days' may be set to 29 by directly writing into it using the `execute address' function. Leap-years must be tracked by the system software.
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
7.5 Power on/power fail detection
PCF8573
If the voltage VDD - VSS1 falls below a certain value the operation of the clock becomes undefined. Thus a warning signal is required to indicate that faultless operation of the clock is not guaranteed. This information is latched in a flag called POWF (Power Fail) and remains latched after restoration of the correct supply voltage until a write procedure with EXECUTE ADDRESS has been received. The flag POWF can be set by an internally generated power fail level-discriminator signal for application with (VDD - VSS1) greater than VTH1, or by an externally generated power fail signal for application with (VDD - VSS1) less than VTH1. The external signal must be applied to the input PFIN. The input stage operates with signals of slow rise and fall times. Internally or externally controlled POWF can be selected by input EXTPF as shown in Table 2. Table 2 Power fail selection PFIN(1) 0 1 0 1 test mode power fail is sensed externally no power fail sensed FUNCTION power fail is sensed internally
The external power fail control operates by absence of the VDD - VSS2 supply. Therefore the input levels applied to PFIN and EXTPF must be within the range of VDD-VSS1. A LOW level at PFIN indicates a power fail. POWF is readable via the I2C-bus. A power-on reset for the I2C-bus control is generated on-chip when the supply voltage VDD - VSS2 is less than VTH2. 7.6 Interface level shifters
EXTPF(1) 0 0 1 1 Note
The level shifters adjust the 5 V operating voltage (VDD - VSS2) of the microcontroller to the internal supply voltage (VDD - VSS1) of the clock/calendar. The oscillator and counter are not influenced by the VDD - VSS2 supply voltage. If the voltage VDD - VSS2 is absent (VDD = VSS2) the output signal of the level shifter is HIGH because VDD is the common node of the VDD - VSS2 and the VDD - VSS1 supplies. Because the level shifters invert the input signals, the internal circuit behaves as if a LOW signal is present on the inputs. FSET, SEC, MIN and COMP are CMOS push-pull output stages. The driving capability of these outputs is lost when the supply voltage VDD - VSS2 = 0.
1. 0 = VSS1 (LOW); 1 = VDD (HIGH).
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
8 CHARACTERISTICS OF THE I2C-BUS
PCF8573
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer (see Fig.3)
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals.
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.3 Bit transfer.
8.2
Start and stop conditions (see Fig.4)
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.4 Definition of start and stop conditions.
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
8.3 System configuration (see Fig.5)
PCF8573
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'.
SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER
MBA605
SLAVE RECEIVER
MASTER TRANSMITTER
Fig.5 System configuration.
8.4
Acknowledge (see Fig.6)
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition, see Figs. 9 and 10.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION
MBC602
1
2
8
9
clock pulse for acknowledgement
Fig.6 Acknowledgment on the I2C-bus.
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
9 9.1 I2C-BUS PROTOCOL Addressing
PCF8573
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.7. Bits A0 and A1 correspond to the two hardware address pins A0 and A1. Connecting these to VDD or VSS allows the device to have 1 of 4 different addresses.
Fig.7 Slave address.
9.2
Clock/calendar READ/WRITE cycles
The I2C-bus configuration for different clock/calendar READ and WRITE cycles is shown in Figs 8, 9 and 10. The write cycle is used to set the time counter, the alarm register and the flags. The transmission of the clock/calendar address is followed by the MODE-POINTER-word which contains a CONTROL-nibble (Table 3) and an ADDRESS-nibble (Table 4). The ADDRESS-nibble is valid only if the preceding CONTROL-nibble is set to EXECUTE ADDRESS. The third transmitted word contains the data to be written into the time counter or alarm register.
Fig.8 Master transmitter transmits to clock/calendar slave receiver.
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
Fig.9 Master transmitter reads clock/calendar after setting mode pointer.
(1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave.
Fig.10 Master reads clock/calendar immediately after first byte.
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
Table 3 BIT 8 0 0 0 0 0 0 0 Note MODE-POINTER-word, CONTROL-nibble (bits 8, 7, 6 and 5) C2 0 0 0 0 1 1 1 C1 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 execute address read control/status flags FUNCTION
PCF8573
reset prescaler, including seconds counter; without carry for minute counter time adjust, with carry for minute counter (note 1) reset NODA flag set NODA flag reset COMP flag
1. If the seconds counter is below 30 there is no carry. This causes a time adjustment of max. -30 s. From the count 30 there is a carry which adjusts the time by max. +30 s. Table 4 BIT 4 0 0 0 0 0 0 0 0 MODE-POINTER-word, ADDRESS-nibble (bits 4, 3, 2 and 1) B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 time counter hours time counter minutes time counter days time counter months alarm register hours alarm register minutes alarm register days alarm register months ADDRESSED TO:
At the end of each data word the address bits B1, B0 will be incremented automatically provided the preceding CONTROL-nibble is set to EXECUTE ADDRESS. There is no carry to B2. Table 5 shows the placement of the BCD upper and lower digits in the DATA byte for writing into the addressed part of the time counter and alarm register respectively. Table 6 shows the acknowledgement response of the clock calendar as a slave receiver. Table 5 MSB UPPER DIGIT UD X X X X Note 1. `X' is the don't care bit; `D' is the data bit. UC X D X X UB D D D X UA D D D D LD D D D D Placement of BCD digits in the DATA byte; note 1 DATA LOWER DIGIT LC D D D D LB D D D D LA D D D D hours minutes days months ADDRESSED TO: LSB
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
Acknowledgement response of the PCF8573 as slave-receiver is shown in Table 6. Note that data is only associated with the `execute address' function where C0, C1, C2 = 0, 0, 0. Table 6 Slave receiver acknowledgement; note 1 MODE POINTER BIT 8 0 0 0 0 0 0 0 0 0 1 Note 1. `X' is `don't care'. To read the addressed part of the time counter and alarm register, plus information from specified control/status flags, the BCD digits in the DATA byte are organized as shown in Table 7. The status of the CONTROL-nibble of the MODE-POINTER-WORD (C2, C1, C0) remains unchanged until re-written. Table 7 MSB UPPER DIGIT UD 0 0 0 0 0 Note 1. `D' is the data bit; `m' = minutes; `s' = seconds. UC 0 D 0 0 0 UB D D D 0 0 UA D D D D m LD D D D D s LC D D D D NODA Organization of the BCD digits in the DATA byte; note 1 DATA LOWER DIGIT LB D D D D COMP LA D D D D POWF ADDRESSED TO: hours minutes days months control/status flags LSB C2 0 0 0 0 0 1 1 1 1 X C1 0 0 0 1 1 0 0 1 1 X C0 0 0 1 0 1 0 1 0 1 X BIT 4 0 1 X X X X X X X X B2 X X X X X X X X X X B1 X X X X X X X X X X B0 X X X X X X X X X X ACKNOWLEDGE ON BYTE: ADDRESS yes yes yes yes yes yes yes yes yes yes MODE POINTER yes no yes yes yes yes yes yes no no DATA yes no no no no no no no no no
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD - VSS1 VDD - VSS2 Vl PARAMETER supply voltage (pin 16 to pin 15) supply voltage (pin 16 to pin 8) input voltage pins 4 and 5 (with input impedance of minimum 500 ) VSS2 - 0.8 pins 6, 7, 13 and 14 any other pin Il IO Ptot PO Tamb Tstg DC input current DC output current total power dissipation per package power dissipation per output operating ambient temperature storage temperature VSS1 - 0.6 VSS2 - 0.6 - - - - -40 -55 VDD + 0.8 VDD + 0.6 VDD + 0.6 10 10 200 100 +85 +125 -0.3 -0.3 MIN. +8.0 +8.0
PCF8573
MAX. V V V V V
UNIT
mA mA mW mW C C
11 HANDLING Inputs and outputs are protected against electrostatic charge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under "Handling MOS Devices".
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
12 DC CHARACTERISTICS VSS2 = 0 V; Tamb = -40 to + 85 C unless otherwise specified. Typical values at Tamb = 25 C. SYMBOL Supply VDD - VSS2 supply voltage (I2C interface) VDD - VSS1 supply voltage (clock) ISS1 supply current at VSS1 (pin 15) supply current at VSS2 (pin 8) LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = VSS2 or VDD tHD; DAT 300 ns see Fig.11 VDD - VSS1 = 1.5 V VDD - VSS1 = 5 V ISS2 VDD - VSS2 = 5 V; IO = 0 all outputs - - - -3 -12 - -10 -50 -50 2.5 1.1 5.0 1.5 6.0 PARAMETER CONDITIONS MIN. TYP.
PCF8573
MAX.
UNI T
V V A A A
VDD - VSS2
Input SCL, input/output SDA VIL VIH ILI Ci VIL VIH ILI VIL VIH ILI - 0.7VDD -1 - - 0.7VDD VI = VSS2 or VDD -250 0 VI = VSS1 to VDD VI = VSS1 to VDD; Tamb = 25 C Output SDA (n channel open-drain) VOL ILI LOW level output voltage input leakage current output ON; IO = 3 mA; VDD - VSS2 = 2.5 to 6 V VDD - VSS2 = 6 V; VO = 6 V VDD - VSS2 = 2.5 V; IO = 0.3 mA VDD - VSS2 = 4 to 6 V; IO = 1.6 mA VOH HIGH level output voltage VDD - VSS2 = 2.5 V; IO = -0.1 mA VDD - VSS2 = 4 to 6 V; IO = -0.5 mA - -1.0 - - 0.4 +1.0 V A -1.0 -0.1 - - - - - - - - - - 0.3VDD - +1 7 V V A pF
Inputs A0, A1, TEST LOW level input voltage HIGH level input voltage input leakage current 0.2VDD - +250 V V nA
Inputs EXTPF, PFIN LOW level input voltage HIGH level input voltage input leakage current 0.2VDD - VSS1 V - +1.0 +0.1 V A A 0.7VDD - VSS1 -
Output SEC, MIN, COMP, FSET (normal buffer outputs) VOL LOW level output voltage - - VDD - 0.4 VDD - 0.4 - - - - 0.4 0.4 - - V V V V
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNI T
Internal threshold voltages VTH1 VTH2 Power failure detection Power-on reset 1 1.5 1.2 2.0 1.4 2.5 V V
handbook, halfpage
-12
MGL072
ISS1 (A) -8
-4
0 0 2 4 VDD-VSS1 (V) 6
Fig.11 Typical supply current (ISS1) as a function of clock supply voltage (VDD - VSS1) at Tamb = -40 to +85 C.
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
13 AC CHARACTERISTICS VSS2 = 0 V; Tamb = -40 to +85 C unless otherwise specified. Typical values at Tamb = +25 C. SYMBOL PARAMETER CONDITIONS - - - - - - MIN. - - - - - - TYP.
PCF8573
MAX.
UNIT s s s s s s
Rise and fall times of input signals tr rise time input EXTPF input PFIN all other inputs (levels between VIL and VIH) tf fall time input EXTPF input PFIN all other inputs (levels between VIL and VIH) Oscillator Cosc Rf fosc integrated oscillator capacitance oscillator feedback resistance oscillator stability (VDD - VSS1) = 100 mV; Tamb = 25 C; (VDD - VSS1) = 1.55 V - - - 40 3 2 x 10-7 - - - pF M 1 1 1 0.3
Quartz crystal parameters (f = 32.768 kHz) Rs CL CT series resistance parallel load capacitance trimmer capacitance - - 5 - - 4.7 4.7 4.0 4.7 4.0 - - 250 0 - 4.0 - 10 - - - - - - - - - - - - - - 40 - 25 k pF pF
I2C-bus timing (see Fig.12; notes 1 and 2) fSCL tSP tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO Notes 1. All timing values are valid within the operating supply voltage and ambient temperature range and reference to VIL and VIH with an input voltage swing of VSS to VDD. 2. A detailed description of the I2C-bus specification, with applications, is given in brochure "The I2C-bus and how to use it". This brochure may be ordered using the code 9398 393 40011. SCL clock frequency tolerable spike width on bus bus free time START condition set-up time START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid STOP condition set-up time 100 100 - - - - - 1.0 0.3 - - 3.4 - kHz ns s s s s s s s ns ns s s
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
handbook, full pagewidth
PROTOCOL
START CONDITION (S)
BIT 7 MSB (A7)
BIT 6 (A6)
BIT 0 LSB (R/W)
ACKNOWLEDGE (A)
STOP CONDITION (P)
t SU;STA
t LOW
t HIGH
1 / f SCL
SCL
t
BUF
tr
tf
SDA
t HD;STA
t SU;DAT
t
HD;DAT
t VD;DAT
MBD820
t SU;STO
Fig.12 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
14 APPLICATION INFORMATION
PCF8573
Fig.13 Application example of the PCF8573 clock/calendar with battery backup.
Fig.14 Application example of the PCF8573 with common VSS1 and VSS2 supply.
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
15 PACKAGE OUTLINES DIP16: plastic dual in-line package; 16 leads (300 mil); long body
PCF8573
SOT38-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 16 9 MH wM (e 1)
pin 1 index E
1
8
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.7 0.19 A1 min. 0.51 0.020 A2 max. 3.7 0.15 b 1.40 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 21.8 21.4 0.86 0.84 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.10 e1 7.62 0.30 L 3.9 3.4 0.15 0.13 ME 8.25 7.80 0.32 0.31 MH 9.5 8.3 0.37 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT38-1 REFERENCES IEC 050G09 JEDEC MO-001AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-10-02 95-01-19
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
PCF8573
SO16: plastic small outline package; 16 leads; body width 7.5 mm
SOT162-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp L 1 e bp 8 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 10.5 10.1 0.41 0.40 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT162-1 REFERENCES IEC 075E03 JEDEC MS-013AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-24
1997 Mar 28
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Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
16 SOLDERING 16.1 Introduction
PCF8573
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 16.2 16.2.1 DIP SOLDERING BY DIPPING OR BY WAVE
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 16.3.2 WAVE SOLDERING
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.3.3 REPAIRING SOLDERED JOINTS
The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 16.2.2 REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 16.3 16.3.1 SO REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Mar 28
21
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF8573
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Mar 28
22
Philips Semiconductors
Product specification
Clock/calendar with Power Fail Detector
NOTES
PCF8573
1997 Mar 28
23
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/03/pp24
Date of release: 1997 Mar 28
Document order number:
9397 750 01674

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